Electronic devices or systems that employ memory typically organize memory components into a memory subsystem. Within most memory subsystems, a device (such as a microprocessor, microcontroller, digital signal processor, memory controller or other device) configured to read data from a memory is coupled to a plurality of memory devices by a data bus.
FIG. 1a shows an exemplary portion of a memory subsystem having a Rambus ASIC Cell (RAC) 105 configured to read data from a plurality of memory devices. For simplicity, FIG. 1a only shows two memory devices D4, D24 coupled to the RAC 105 by a single data line 104. However it is to be understood that in typical memory subsystem architectures, data line 104 is normally associated with a larger data bus that couples more than the two memory devices D4, D24 shown in FIG. 1a. 
Within each memory device D4, D24 an output driver circuit is shown that is responsible for driving data from its associated memory device to the RAC 105. Referring to the output driver circuit within memory device D4, note that the designed for signal levels driven by this circuit are 1.8v at one logic level (e.g., “0”) and 1.0v at another logic level (e.g., “1”). Note that those of ordinary skill could design other driver circuit embodiments where a logic level of “1” corresponds to a higher voltage than a logic level of “0”.
When the logic level to be read from memory device D4 is a logic low, all drivers Q1 through Qn are “off” (i.e., both transistors within each driver are in cutoff). Because no current flows through load resistor 103, the voltage appearing on data line 104 is 1.8v. When the logic level to be read from memory device D4 is a logic high, one or more drivers Q1 through Qn are “on” (i.e., both transistors within an “on” driver are active) which pulls current through load resistor 103 and lowers the voltage on data line 104.
A feedback loop having a comparator 101 and counter 102 automatically configures the number of “on” drivers to correspond to an output voltage level of 1.0v for logic high outputs. For each driver that is on more total current is pulled through load resistor 103. If the total current corresponds to a voltage on data line 104 below 1.0v, comparator 101 produces a negative output causing counter 102 to countdown.
The countdown activity of counter 102 turns drivers “off” (e.g., drivers Qn and Qn−1) that were originally “on” until the drop in total current pulled through load resistor 103 corresponds to a resulting increase in data line 104 voltage to the proper voltage of 1.0v. When the proper voltage is reached, the comparator 101 output becomes neutral (signifying the feedback loop is in a steady state and) causing the countdown activity to stop. A device's feedback circuit typically operates during a set aside calibration period rather when its data is actually being read.
Similarly, if the total current pulled by all “on” drivers corresponds to a voltage on data line 104 above 1.0v, the comparator 101 output becomes positive causing counter 102 to count up. The countup activity of counter 102 turns “off” drivers “on” until the increase in total current pulled through load resistor 103 corresponds to a resulting decrease in data line 104 voltage to the proper voltage. When the proper voltage is reached, the comparator 101 output becomes neutral (signifying the feedback loop is in a steady state and) causing the countup activity to stop.
A problem associated with memory subsystems designed according to the above described approach occurs during a “back-to-back” read. An example of a back-to-back read is shown in FIG. 1b. In a back-to-back read, two memory devices are read—one after the other. Thus, in FIG. 1b, device D24 is read just before device D4 is read. In order to hasten the timing between back to back reads, memory devices may be read on the rising 106 and falling 107 edges of the same clock as also seen in FIG. 1b. 
During back to back reads of a logic high signal, where the second read corresponds to the memory device D4 that is closer to the reading device 105, signal integrity along data line 104 may be flawed as seen in FIG. 1c. FIG. 1c is a “zoom in” of the transition 114 between the D24 read interval 116 and the D4 read interval 117.
An ideal back-to-back read of logic high data appears as two 1.0v pulses separated by a drop to a reduced voltage 115. At approximately the moment in time 119 that the closest device D4 turns its drivers “on”, the farther device D24 also turns its drivers “off”. However, because the effect of the farther device D24 having its drivers turned “off” is not seen until a propagation time 108 later (that is proportional to the length of the data line 104 trace between memory device D4 and D24), the voltage on data line 104 behaves as if both devices D4 and D24 are actively pulling current.
Thus, the reduced voltage 115 corresponds to the voltage resulting from both memory devices (e.g., both D4 and D24) effectively having “on” drivers. The reduced voltage 115 should last until a propagation time 108 later when the effect of D24's turning of its drivers “off” is observed and the voltage on data line properly rises back to 1.0v.
In many cases, however, the ideal signal just described does not result. Instead of dropping to reduced voltage 115 when device D4 turns its drivers on the data line 104 voltage gradually decays as observed in trace 120. When the effect of the deactivation of D24's drivers is observed (propagation time 108 later), the data line 104 voltage jumps to an elevated level 118 as observed in trace 109. In some instances the difference 110 between elevated voltage 118 and 1.0v is sufficient to cause D4 read being improperly read as a logic “low” (e.g., 1.4v or higher) rather than a logic “high”.
Thus a flawed signal 120, 109 (shown in FIG. 1c) may be observed along a data line 104 undergoing a back-to-back read. The cause of the flawed signal 120, 109 is related to the Ids v. Vds characteristics of the transistors within the drivers Q1 through Qn that are turned on at time 119. Specifically, the transistors exhibit a reduced output impedance as the voltage on data line 104 drops.
Output impedance is the inverse of the slope of the Ids v. Vds curve. More generically, high output impedance is characterized by a substantially level portion of the transistor curve while low output impedance is characterized by a substantially sloped portion of the transistor curve. For field effect transistors, Ids is a transistor's drain to source current while Vds is a transistor's drain to source voltage. Thus, referring to the typical Ids v. Vds curve 113 shown in FIG. 1d, high output impedance is observed in curve region 111 (having near zero slope) while low output impedance is observed in curve region 112 (having significant slope). Note the transition between the low 112 and high 111 output impedance regions occurs at a Vds voltage of Vx. Vx is the Vds voltage where velocity saturation is approximately reached.
If Vx is approximately 1.0v, the output impedance of the driver transistors will drop as the voltage on data line 104 falls below 1.0v. That is, as the voltage on data line 104 continually falls below 1.0v, the driver transistors continually pull less and less current. As such, at moment 119 when D4's drivers are turned on, the transistors within these drivers will pull less and less current as the voltage on data line 104 falls. Hence signal 120 correlates to the falling of curve 113 within region 112.
Thus, for driver transistors having a Vx near 1.0v, the signal integrity problem discussed with respect to FIG. 1c is related to the decay of the driver transistors' output impedance.